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1996-2000 [1996.11.__] Wafer Engineering for DRAM Devices

2019.04.02 19:57

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Wafer Engineering for DRAM Devices

Defect Engineering in Submicron Process Technologies

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번호	제목
27	[1999.01.01] Novel electron mobility model for n-HgCdTe
26	[1999.01.01] Effect of crystal defects such as COPs, Large dislocations, and OSF-ring on device integrity degradation
25	[1998.__.__] COP induced oxide breakdown decorated by Cu in CZ Si
24	[1998.__.__] Challenge of Material Properties for 300mm Wafers
23	[1998.09.28] Wafer Requirements : Memory Devices SEMI SILICON WAFER SYMPOSIUM
22	[1997.__.__] Effect of Crystal Defects on Device Characteristics
21	[1997.__.__] 300mm Wafer Technology
20	[1997.10.08] Ni/3C-SiC 계면의 Ohmic 특성
19	[1996.__.__] Effect of Crystal Characteristics on the DRAM Device Yield
18	[1996.__.__] DRAM Wafer Qualification Issues : Oxide integrity vs. D-Defects, Oxygen Precipitates and High Temperature Annealing
»	[1996.11.__] Wafer Engineering for DRAM Devices
16	[1996.11.25] Effect of Crystal Defects on Device Characteristics
15	[1995.__.__] Observation of Structural, Electrical, and Chemical Nature on Multi-ring Wafer
14	[1995.__.__] Nature of D-defect in CZ Silicon : D-defect Dissolution and D-Defect Related T.D.D.B
13	[1995.__.__] Gate Oxide Integrity in DRAM Devices : The Influence of Substrate D-defects

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