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공지 Update 진행중
107 [2004.10.__] Effect of Ge mole fraction and Strained Si Thickness on Electron Mobility of FD n-MOSFET Fabricated on Strained Si/Relaxed SiGe/SiO2/Si file
106 [2004.10.__] Determination of the distribution and morphology of silicon islands in the buried oxide layer of SOI wafers by using a focused ion beam and transmission electron microscope file
105 [2004.10.31] 나노 스케일 C-MOSFET에 적용되는 완충된 SiGe층 위에 성장된 나노스케일 변위 실리콘층을 가지는 SOI C-MOSFET file
104 [2004.10.28] Effect of Strained Si Thickness on Electron Scattering Rate in n-MOSFET Fabricated on Strained Si/SiGe/SiO2/Si
103 [2004.10.28] Design and Implementation of the Mobile Disaster Management Application System Based on PDA
102 [2004.10.28] CDS Reliability Test of Contents Aggregater for VOD/NVOD Service.
101 [2004.09.__] Proximity gettering process for 300-mm silicon wafers
100 [2004.09.__] Effect of nano-scale strained Si layer grown on SiGe-on-insulator structure on MOSFET drain current improvement
99 [2004.08.__] Nature of Surface and Bulk Defects Induced by Epitaxial Layer Growth in Epitaxial Transfer Wafers file
98 [2004.08.16] A Study on the Optimization of the Layout for the ESD Protection Circuit in 0.18µm CMOS Silicide Process
97 [2004.08.15] Effect of molecular weight of surfactant in nano ceria slurry on shallow trench isolation chemical mechanical polishing (CMP) file
96 [2004.08.10] Dependency of precipitation of interstitial oxygen on its crystal nature in Czochralski silicon wafer file
95 [2004.08.01] Nanotopography impact in shallow trench isolation chemical mechanical polishing-dependence on slurry characteristics
94 [2004.08.01] Achievement of nano-scale SiGe layer with discrete Ge mole fraction profile using batch-type HVCVD
93 [2004.07.09] Nanotopography Simulation of Shallow Trench Isolation Chemical Mechanical Polishing using Nano Ceria Slurry